1. Field of the Invention
The present invention relates to a charge pump circuit that raises a voltage by use of a combination of a capacitor and a switch.
2. Description of Related Art
A charge pump circuit is used, for example, as a voltage raising circuit (voltage step-up circuit) in a non-volatile storage device or a DC/DC switching regulator. In particular in recent years, as mobile devices such as smartphones and notebook personal computers are increasingly widespread, circuits used in such mobile devices are required to be compact and power-saving. A charge pump circuit, which achieves voltage raising without using an inductor, is suitable for size reduction.
As a so-called high-side switching device, that is, a switching device that is arranged on the supply line side of a DC/DC switching regulator, either a PMOS transistor or an NMOS transistor, for instance, is commonly used. A PMOS transistor has the advantage of comparatively easy gate voltage control, but has the disadvantage of requiring a larger area than an NMOS transistor to obtain comparable electrical characteristics, leading to higher production cost. Moreover, a low ON-state resistance, which is difficult to achieve with a PMOS transistor, can be achieved with an NMOS transistor with about one-third of the area that would be required with a PMOS transistor, leading to reduced production cost. However, using an NMOS transistor as a high-side switching device requires, to drive its gate, a voltage raising circuit such as a charge pump circuit or a bootstrap circuit; inconveniently, this results in increased current consumption and a higher withstand voltage in transistors.
FIG. 9 is a diagram illustrating the basic operation of a commonly known charge pump circuit. The charge pump circuit 100 is composed of a switching device SW, which is an NMOS transistor, and a voltage raiser 2. The switching device SW has a drain D, a source S, and a gate G. An input voltage vin is supplied to the source S of the switching device SW and to an input terminal Ti of the voltage raiser 2. The input voltage vin is supplied also to the source S of the switching device SW. From a raised output terminal TCP of the voltage raiser 2, a raised output voltage vcp which is higher than the input voltage vin by the threshold voltage Vt of the switching device SW is output, and the raised output voltage vcp is applied to the gate G of the switching device SW. The raised output voltage vcp is a voltage that is higher than the input voltage vin by 5 V to 6 V. For example, when the input voltage vin is set at 19 V, the raised output voltage vcp is set at, for example, 25 V (19 V+6 V=26 V). Thus, the switching device SW can be reliably brought into an ON state. This means that, in a case where the switching device SW is an NMOS transistor, a voltage that is higher than the input voltage vin by several volts has to be applied to its gate. Thus, using an NMOS transistor on the supply line side, on one hand, provides benefits as mentioned above but, on the other hand, leaves problems in terms of how to reduce power consumption and how to increase the switching device's withstand voltage.
As charge pump circuits, there have conventionally been proposed various configurations to suit different purposes. One known for power saving is seen in, for example, Japanese Patent Application Published No. 2001-112239 (hereinafter referred to as Patent Document 1). According to Patent Document 1, while the frequency of a clock fed to the charge pump circuit is constant, the raised voltage is controlled properly. To that end, when the output voltage of the charge pump circuit is lower than the desired voltage, a first or second clock starts to be supplied, and when the output voltage is higher than the desired voltage, the first or second clock stops being supplied.
According to Japanese Patent Application Publication No. 2002-233135 (hereinafter referred to as Patent Document 2), for efficient power consumption, there is provided a variable frequency generator for varying the frequency of an input signal to the charge pump circuit. Thus, variation in current load can be coped with properly by varying the frequency of an oscillator.
According to Japanese Patent Application Publication No. H11-328973 (hereinafter referred to as Patent Document 3), a semiconductor storage device is provided that operates with reduced power consumption. To that end, in a semiconductor storage device having a ring oscillator and a voltage raising circuit, the ring oscillator is operated at a short oscillation period until the raised voltage is reached, and the ring oscillator is operated slower, at a short oscillation period, after the completion of voltage raising.
According to Japanese Patent Application Publication No. 2008-124852 (hereinafter referred to as Patent Document 4), a charge pump circuit is provided that operates with lower power consumption. To that end, there is provided an oscillation circuit for supplying a clock signal, and the oscillation circuit has a current generation circuit that controls a ring oscillator having inverters connected in a ring formation and the current passing through the inverters so as to decrease the frequency of the clock signal as a supplied voltage increases.
However, according to Patent Document 1, when the output voltage is higher than the desired voltage, stopping the supply of the clock may cause a large variation in the output voltage, possibly producing an undesired large ripple.
According to Patent Document 2, when the load is heavy, the oscillation frequency is increased and, when the load is light, the oscillation frequency is decreased. Here, if, already at an early stage, the output current is high, that is, the load is heavy, then, already at an early stage, the oscillation frequency is high and accordingly the output voltage is high. This tends to cause a vicious cycle in which a rise in the output voltage results in a rise in the output current, and hence a rise in the oscillation frequency. Thus, the oscillator operates at the maximum frequency all the time, leading to high power loss.
According to Patent Document 3, the period of the clock is varied by varying the number of inverters in the ring oscillator which generates the clock. This requires as many switching devices as the number of inverters that need to be varied. Inconveniently, providing a number of switching devices complicates the circuit for controlling those switching devices.
According to Patent Document 4, controlling the ring oscillator and the current passing through the inverters requires a current generation circuit that decreases the current as the supplied voltage increases. Inconveniently, this requires a somewhat complicated circuit and, as the number of stages of inverters increases, accordingly increased current adjustment accuracy.